2023-03-13T11:35:10-04:00 X, The Moonshot Factory
CMOS ASIC Design Lead
Hardware Engineering
Mountain View, CA (HQ)

X is Alphabet’s moonshot factory. We are a diverse group of inventors and entrepreneurs who build and launch technologies that aim to improve the lives of millions, even billions, of people. Our goal: 10x impact on the world’s most intractable problems, not just 10% improvement. We approach projects that have the aspiration and riskiness of research with the speed and ambition of a startup.

About the Team:

At X Project Taara is developing free space optical communication link to bring affordable internet to developing countries: https://x.company/projects/taara/ 

Project Taara is focused on delivering high-throughput and long-range connectivity via free-space optical communication (FSOC) links that uses light (eye-safe lasers) propagating between two terminals to wirelessly transmit high speed data (upto 20 Gbps). It can connect two points upto 10 km apart and has a few unique advantages over traditional fiber:

  • Avoids challenges associated with trenching or securing permitting rights
  • Costs a fraction of what it would to deploy underground cables & can be installed in a few hours
  • Operates in the unlicensed spectrum and, therefore, bypasses licensing fees; it is also immune to interference issues that other unlicensed alternatives face

The Taara Project is seeking a Senior Integrated Circuit engineer leading the next generation circuit design as part of the R&D team developing cutting-edge wireless optical communication systems.  

About the Role:

The successful candidate will lead the application specific integrated circuit (ASIC) development from concept to product.  The position seeks highly-motivated individuals that enjoy working in a small dynamic team environment, with a passion for solving challenging problems that can lead to high-impact advances in technology.  The candidate will contribute to the detailed circuit design and lead a small team of internal resources and external vendors. 

The CMOS design will include analog mixed signal, radio frequency focused and digital design for free-space optical communication links including; analog frontend, precision D/A and A/D converters, high speed serializer/deserializer, clock and bias generation/distribution, and digital signal processing backend circuits.

How you will make 10X impact:

  • Develop, in collaboration with other leads, a comprehensive roadmap for on-chip-integration of wireless optical communications products towards 100x improvements to cost and scale relative to the state of the art.
  • Support identifying and managing key design, fabrication, test and packaging vendors
  • Responsible for design-process development, managing new product introduction for technology, and leading foundry process bring-up
  • Set strategy for packaging and assembly planning and engagements for complex assemblies integrating the circuit with photonics integrated circuits and thermal management.
  • Plan and track technology and foundry roadmaps to determine appropriate technology strategies.
  • Motivated by making the world a better place through technology, and wanting to be part of a team that makes this happen
  • Mentor and coach other team members with regards to process technology

What you should have:

  • MS Electrical Engineering or related field
  • Experience as a top-level chip owner and extensive tapeout experience including successful bring-up and testing of a mixed-signal SoC.
  • Excellent communication and presentation skills (writing strategy docs, writing and delivering presentations), can work with senior external partners with ease
  • Highly proficient in the use of standard IC design tools (Cadence Virtuoso, Innovus, etc.) and methodologies. Able to drive a design from schematic/RTL through layout and verification.
  • CAD tool setup and debugging know-how to and ability to build the ASIC infrastructure
  • Experience with production-grade design verification including Monte-Carlo and corner simulations and EM/IR analysis of analog or digital blocks.
  • Familiarity with IC and photonics packaging technology and ability to evaluate the impact of different packaging techniques on system performance and cost. Experience with flip-chip packaging, interposer design, and working with vendors to get chips packaged.

It’d be great if you also had these:

  • Ph.D. Electrical Engineering or related field
  • Experience leading teams 
  • Proficiency with Python and Git.
  • Experience with integrated photonics design and/or co-design of electronics and photonics, especially in monolithic electronics/photonics process nodes.

The US base salary range for this position is $188,000 - $197,000 + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include benefits.

At X, we don't just accept difference - we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. We are proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.

If you have a disability or special need that requires accommodation, please contact us at: x-accommodation-request@x.team.

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